--===========================================================================--
-- Naziv		:  System
-- Ime fajla	: system.vhd  
-- Verzija		: 0.1
--===========================================================================-- 

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity system is 
	  
end;

architecture system_AR of system is
--Komponente:
	--pipeline
	component pipeline is 
		  port (
			--IN
				mrReset,clk,clk2 : in  std_logic ;				
			--INOUT				
				I_DBUS : in std_logic_vector (15 downto 0); --Data magistrala za instrukcije 
				D_DBUS : inout std_logic_vector (15 downto 0); --Data magistrala za podatke
			--OUT	
				I_RD : out std_logic;
				I_ABUS : out std_logic_vector (15 downto 0); --Adresna magistrala za instrukcije 
				D_RD, D_WR : out std_logic;
				D_ABUS : out std_logic_vector (15 downto 0) --Adresna magistrala za podatke
			
			);
   end component;
	------
	component IMem is 	
	PORT
      (	
		   clk		: IN STD_LOGIC ;
		   addr		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		   q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
		   
	   );
   end component;
    
    
   component test_mem is 	
	PORT
      (	
		   address		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		   clock		: IN STD_LOGIC ;
   		   rden		: IN STD_LOGIC ;
		   q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
		   
	   );
    end component;
    
    
 component test_dmem IS
	PORT
	(
		address		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		clock		: IN STD_LOGIC ;
		data		: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
		wren		: IN STD_LOGIC ;
		rden		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
	);
   END component;
	--------

--Signali
	--read,write
	signal I_RD , D_RD ,D_WR, clk, clk2, mrReset :  std_logic;
	signal I_ABUS, I_DBUS, D_ABUS, D_DBUS: std_logic_vector (15 downto 0);
	
	
begin
   
   clock_PR: process
   begin
       if clk = '1' then
           clk <= '0';
        else
           clk <= '1';
       end if;
       wait for 40 ns;
   end process clock_PR;
   
   clock2_PR: process
   begin
       clk2 <= '0';
       wait FOR 20 ns;
       while true loop
          if clk2 = '1' then
              clk2 <= '0';
           else
              clk2 <= '1';
          end if;
          wait for 40 ns;
         end loop;
   end process clock2_PR;
   
   reset_PR: process
   begin
       mrReset <= '1';
       wait for 100 ns;
       mrReset <= '0';
       wait;
   end process reset_PR;
   
	--povezivanje pipeline
	  pipeline_map : pipeline PORT MAP (mrReset,clk,clk2,I_DBUS,D_DBUS,I_RD,I_ABUS,D_RD,D_WR,D_ABUS);
     
	--IMem_inst : IMem PORT MAP (
		--addr	 => I_ABUS,
		--clk	 => clk2,
		--q	 => I_DBUS
	--);
	
	test_mem_inst : test_mem PORT MAP 
   (
		address	 => I_ABUS,
		clock	 => clk2,
		rden		=> I_RD,
		q	 => I_DBUS
	);
	
	test_dmem_inst : test_dmem PORT MAP
	(
		address		=> D_ABUS,
		clock		=> clk2,
		data		=> D_DBUS,
		wren		=> D_WR,
		rden		=> D_RD,
		q	=> D_DBUS
	);

	
end system_AR;


